The present invention relates to a semiconductor memory device having a plurality of memory cells of single transistor type, and more particularly to a memory cell having a trench capacitor.
A new single transistor type memory cell constituted by one transistor and one storage capacitor was proposed in TECHNICAL DIGEST OF IEDM, 1984, pp 240 to 243, by S. Nakajima et al. entitled "AN ISOLATION-MERGED VERTICAL CAPACITOR CELL FOR LARGE CAPACITY DRAM". In the memory cell, a trench for forming the capacitor is provided in a semiconductor substrate having a uniform impurity concentration from the major surface into the inner portion thereof, and surrounds the transistor forming region of the substrate. A cell plate is provided in the trench and capacitor electrodes are provided between the side walls of the trench and the cell plate, respectively, such that a first MOS capacitor is formed between the side wall of the trench and the capacitor electrode, and a second MOS capacitor is formed between the capacitor electrode and the cell plate. Source and drain regions of the transistor are formed in the transistor forming region surrounded by the trench. One of the source and drain regions is connected to the capacitor electrode at an upper side portion of the trench and the other of the source and drain regions is connected to a bit line at a surface portion located within the surface of the transistor forming region and separated from the trench.
The memory cell can realize a large amount of storage capacitance because the first and second MOS capacitors surround the transistor forming region. The cell plate, to which a constant voltage such as ground potential is applied, surrounds each memory cell. Therefore, an interference between memory cells can be avoided even if a conventional thick field insulating layer would not be formed therebetween.
However, in the memory cell, the bit line is connected to the source or drain region of the transistor at the portion which is located within the surface of the transistor forming region and separated from the trench. Therefore, a miniaturization of the memory cell in more extent, that is, a higher integration of the memory device cannot be realized. Further, the impurity concentration of the substrate cannot be a high level because of obtaining a necessary breakdown voltage of the PN junction between the source, drain regions and the substrate. In this case, an inversion layer are apt to produce along the side wall of the trench when a high voltage is applied to the capacitor electrode. Consequently, the information reservation characteristic of the memory cell is deteriorated by a leakage current between the inversion layer and the bit line via the source or drain region to which the bit line is connected.